1. Field of the Invention
This invention relates to an electrically rewritable and non-volatile semiconductor memory device (EEPROM).
2. Description of Related Art
A cell array of a NAND-type flash memory, which is known as an EEPROM, is formed of NAND cell units arranged therein, each NAND cell unit having plural memory cells connected in series. One end of each NAND cell unit is connected to a bit line, and the other to a source line. Control gates of the memory cells in the NAND cell unit are connected to different word lines.
In such the NAND type flash memory, since plural memory cells are connected in series in such a manner that each source/drain is shared with adjacent two memory cells, and bit line contacts and source line contacts are shared with plural memory cells, it is possible to achieve a small unit cell size. In addition, it is suitable for miniaturizing the memory chip that word lines and device regions are formed with substantially simple stripe patterns in the cell array, whereby large capacitive flash memories have already been achieved.
Further, data write or erasure of the NAND type slash memory may be performed by simultaneously causing many cells to flow FN tunneling current. In detail, supposing that a group of memory cells sharing a word line serves as one page or two pages, data write is done by a page. Data erasure is done by a block which is defined as a group of NAND cell units sharing word lines and select gate lines. On the other hand, one page data are serially transferred between a sense amplifier circuit, which stores one page read or write data, and an I/O terminal. Due to these specifications, NAND flash memories have already been accepted in the market as having an excellent performance for use of storing in a non-volatile manner large capacitive and continuous data such as still image, moving image, music data and the like.
With respect to the block erasure of the NAND type flash memory, it is necessary to do verify-read (i.e., erase-verify) for verifying an erase state in which the threshold voltages of selected memory cells have been shifted into a predetermined threshold range. It has already been proposed an erase-verify scheme in which a NAND cell unit current is carried from the source line to the bit line (for example, refer to Japanese Patent Application Laid Open No. 2003-249083).
Such the method will be explained in detail bellow. In the NAND flash memory, binary data is usually defined by a negative threshold state serving as a “1” data (erase state), and a positive threshold state serving as a “0” data (write state). To verify that memory cells in an erased block are in a threshold state of Vt=−1V, apply 0V to the entire word lines in the block, and apply a power supply voltage Vdd to the source line after having precharged the bit line to 0V. Applied to the select gate lines is a voltage necessary for making the select gate transistors being in a deeply on state.
If all memory cells in the NAND cell unit have been erased to have a threshold voltage Vt equal to or lower than −1V, the channel current flows to charge and boost the bit line to Vg−Vt′=0V−(−1V)=1V. While Vt′ is a threshold voltage of the memory cell in consideration of a substrate bias effect, it is assumed to be Vt=Vt′ here for simplifying the explanation. If there is at least one memory cell, threshold of which is not reduced to −1V (i.e., the memory cell is not sufficiently erased), the bit line voltage is not boosted. Therefore, detect the bit line voltage by the sense amplifier circuit, and it is possible to verify the erase state of the NAND cell unit.
A conventional sense amplifier circuit used in NAND-type flash memories is configured to have precharge circuit for precharging a sense node and a bit line, clamping transistor disposed between the sense node and the bit line to clamping the bit line precharge level, and data latch with a clocked inverter for detecting bit line voltage transferred to the sense node. It has already been proposed a sense amplifier circuit with a boost capacitor connected to the sense node for increasing the sense margin (for example, refer to Japanese Patent Application Laid Open No. 2001-325796).
In the above-described erase-verify scheme adapted to a NAND type flash memory with the conventional sense amplifier, there is a problem that it is difficult to secure a large verify margin. Especially in recent years, it is strongly required to lower the power supply voltage of memories. In practice, a low power supply voltage, such as Vdd=1.8V, is going to be used in memories. Using such the low power supply voltage, the erase-verify margin becomes further smaller.